1. Field of the Invention
The invention relates to memory circuits, and more particularly to memory circuits with sense amplifiers.
2. Description of the Related Art
A memory circuit comprises a memory cell array storing a plurality of data bits. When a memory circuit is read, a control circuit of the memory circuit enables a word line coupled to the memory cell array, and the memory cell array triggered by the word line outputs read data bits to a bit line. The memory cell array, however, has a weak driving ability for driving an output voltage of the memory circuit. Thus, a sense amplifier is used to detect the read data bits on the bit line and generates an output signal according to the read data bits.
Referring to FIG. 1, a schematic diagram of voltage changes of a word line WL, a bit line BL, and a sense amplifier enable signal SAE of a memory circuit is shown. A control circuit first raises the voltage of the word line WL to a high level at time t0 to initiate reading of a memory cell array. The memory cell array then outputs data bits to the bit line BL. When the read data bit is “1”, the voltage of the bit line BL is maintained at a high level 102. When the read data bits is “0”, the memory cell array lowers the voltage of the bit line BL to a low level, as shown by the mark 104. The difference M between the high level 102 and the lowered level is referred to as a read margin.
If the delay time TD between time t0 and time t1 is not long enough, the read margin M may be smaller than the resolution of the sense amplifier, then the sense amplifier will mistakenly recognize the output data bit “0” as a data bit “1”, thus inducing reading errors of the memory circuit. When the delay time TD is extended to increase the read margin M to ensure correctness of data detection of the sense amplifier, access time of the memory circuit is increased. Thus, the delay time and the read margin must be properly determined.
Referring to FIG. 2, a circuit diagram of a sense amplifier 220 of a memory circuit is shown. The sense amplifier 220 comprises two PMOS transistors 228 and 230 and three NMOS transistors 222, 224, and 226. Before a word line is enabled, a pre-charge signal PRE turns on the transistors 202 and 204 to charge voltages of the nodes 206 and 208 to a high voltage VDD. The word line is then enabled to trigger a memory cell array to output data to a bit line BL and a bit line bar BLB. A signal pgB then turns on the transistors 212 and 214 to input the data on the bit line BL and the bit line bar BLB to the nodes 206 and 208. A sense amplifier enable signal SAE is then enabled to turn on the NMOS transistor 226, thus enabling the sense amplifier 220 to detect the data bits on the nodes 206 and 208.
Referring to FIG. 3A, probability distributions of an offset voltage of a sense amplifier and a memory cell current under a higher voltage supply level of 1.2 V is shown. The probability distribution of the offset voltage of the sense amplifier is shown with a solid line, and the probability distribution of a voltage of a bit line affected by the memory cell current is shown with a dotted line. An overlapping portion of the two probability distributions induces reading errors of the sense amplifier. The overlapping section of the two probability distributions means that a cell current of a memory cell array has generated a bit line voltage that can not be detected by a sense amplifier, thus inducing reading errors of the sense amplifier. In other words, a probability of occurrence of reading errors is equal to a convolution of the two probability distribution functions shown in FIG. 3A.
When a voltage level of a voltage source VDD supplied to a memory circuit is lowered, a cell current generated by memory cells of the memory circuit has a reduced level, thus decreasing a read margin of a bit line and negatively affecting correctness of output data generated by a sense amplifier. Referring to FIG. 3B, probability distributions of an offset voltage of a sense amplifier and a memory cell current under a lower voltage supply level of 0.72 V is shown. The overlapped section of the two probability distributions shown in FIG. 3B is enlarged in comparison with that shown in FIG. 3A. Because a probability of occurrence of reading errors is equal to a convolution of the two probability distribution functions, the probability of occurrence of reading errors is increased in FIG. 3B due to lowering of the supplied voltage level. Thus, when a voltage level of a voltage source supplied to a memory circuit is lowered, the sense amplifier may detect data bits with errors, thus generating an erroneous output signal.
Referring to FIG. 4, a block diagram of a conventional tracking circuit 400 generating a sense amplifier enable signal SAE is shown. The tracking circuit 400 is made up of logical gates and comprises a plurality of inverters 402, 404, and 406 and an AND gate 408. The inverters 402, 404, and 406 sequentially invert the voltage of the word line WL. Each of the inverters 402, 404, and 406 delays the signal on the word line WL for a short period. The AND gate 408 then performs an AND operation on the voltage of the word line and the inverted voltage output by the inverter 406 to obtain the sense amplifier enable signal SAE.
An operating voltage of a memory circuit may change in response to different host system applications. When a host system application has a heavy data processing load, a voltage level of a voltage source supplied to the memory circuit may be increased for better performance. When application of the host system has a light data processing load, a voltage level of the voltage source supplied to the memory circuit may be decreased to reduce power consumption. When the voltage level of the voltage source is decreased, because a memory cell array comprises a plurality of cells made up of transistors, the cell currents are reduced due to the decreased voltage level of the voltage source, and the memory cell array has a poorer ability for driving the voltage on the bit line. Thus, a tracking circuit should delay a voltage of a word line for a longer period to generate a sense amplifier enable signal SAE when a supply voltage level is decreased, thus allowing the memory cell array to have a longer time period to discharge the bit line. The tracking circuit 400, however, is made up of logical gates and does not adjust the delay period TD according to different supply voltage levels. Thus, a sense amplifier triggered by a sense amplifier enable signal SAE generated by the conventional tracking circuit 400 generates an output signal with poor accuracy when a voltage level of the voltage source supplied to the memory circuit is decreased.
Referring to FIG. 5A, a block diagram of another conventional tracking circuit 500 generating a sense amplifier enable signal SAE is shown. The tracking circuit 500 comprises a plurality of dummy cells 502˜510 and an inverter 520. Each of the dummy cells has a similar structure as the dummy cell 550 shown in FIG. 5B. The dummy cell 550 comprises two inverters 556 and 558 and two NMOS transistors 552 and 554 with high threshold voltage VT and stores a data bit “0”. The node 562 therefore has a logic low voltage and the node 564 has a logic high voltage. When the word line WL is enabled, the NMOS transistors 552 and 554 are turned on, coupling the node 562 to a dummy bit line DMY_BL and coupling the node 564 to a dummy bit line bar DMY_BLB. Thus, the voltage of the dummy bit line DMY_BL shown in FIG. 5A is gradually lowered to the logic low level by the dummy cells 502˜510 when the word line WL is enabled. The inverter 520 then inverts the voltage of the dummy bit line DMY_BL to obtain the sense amplifier enable signal SAE, which has a delay in comparison with the voltage of the word line due to the weak voltage driving ability of the dummy cells 502˜510.
The plurality of dummy cells 502˜510 are made up of transistors with a high threshold voltage. However, the logic cells in the following delay path, such as the inverter 520, are made up of transistors with a standard threshold voltage. Because a current I flowing through a transistor is in proportion to (VDD−VT)2, wherein VDD is the supplied voltage and VT is the threshold voltage of the transistor, when the supplied voltage VDD is lowered, the current I flowing through a transistor with a high threshold voltage is reduced by a greater amount than a transistor with a standard threshold voltage, thus inducing a greater signal delay. In other words, even though the dummy cells 502˜510 are made up of transistors with a high threshold voltage, when a voltage level of a voltage source supplied to the tracking circuit 500 and the memory cell array is lowered, a delay mismatch between the tracking circuit 500 and the memory cell array would be induced due to the existence of devices with a standard threshold voltage, and performance of the whole memory circuit is degraded. Thus, a tracking circuit of a memory circuit without the aforementioned deficiencies is required.